Enhancing semiconductor structure surface area using hsg and etching

ABSTRACT

A method for forming HSG polysilicon with reduced dielectric bridging and increased capacitance. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a reduced temperature to cause a nucleation of the second polysilicon layer. Grains are formed on the surface of the second polysilicon layer as a result of the nucleation. Next a wet etch is performed to remove portions of the polysilicon grains and portions of the first polysilicon layer. The duration of the wet etch is controlled to retain a roughened surface area. The size of the grains decreases during the wet etch and the distance between the grains increases. A dielectric layer is deposited to overlie the rough polysilicon following the wet etch. The thickness of the dielectric layer tends to be uniform thereby reducing bridging of the dielectric between the grains of the of the polysilicon.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is being filed simultaneously with copendingapplication having disclosure number 93-547 entitled “A METHOD FORINCREASING CAPACITANCE OF AN HSG RUGGED CAPACITOR USING A PHOSPHINE RICHOXIDATION AND SUBSEQUENT WET ETCH.” The two applications may containsimilar material.

FIELD OF THE INVENTION

[0002] This invention relates to semiconductor technology and, morespecifically, to the design of capacitors used in dynamic random accessmemory cells.

BACKGROUND OF THE INVENTION

[0003] The invention uses various materials which are electricallyeither conductive, insulative or semi-conductive, although the completedcircuit device itself is usually referred to as a “semiconductor.”

[0004] The memory cells of dynamic random access memories (DRAMs) arecomprised of two main components: a field-effect transistor and acapacitor. In DRAM cells utilizing a conventional planar capacitor (suchas the one depicted in FIG. 1), far more chip surface area is dedicatedto planar capacitor 11 than to field-effect transistor (FET) 12. Thegate 13 of FET 12 and the word line 14 are formed from an etchedpolycrystalline silicon layer. Bit line 15 connects with access-nodejunction 16. Capacitor 11 has a lower plate formed from the n+ siliconsubstrate extension 17 of storage node junction 18 of FET 12. Uppercapacitor plate (or field plate) 19 is formed from a layer ofconductively-doped polycrystalline silicon. Substrate extension 17 iselectrically insulated from upper plate 19 by a dielectric layer 20.Planar capacitors have generally proven adequate for use in DRAM chipsup to the one-megabit level. However, planar capacitors constructed withconventional dielectric materials appear to be unusable beyond theone-megabit DRAM level. As component density in memory chips hasincreased, the shrinkage of cell capacitor size has resulted in a numberof problems. Firstly, the alpha-particle component of normal backgroundradiation will generate hole-electron pairs in the n+ silicon substrateplate of a cell capacitor. This phenomena will cause the charge withinthe affected cell capacitor to rapidly dissipate, resulting in a “soft”error. Secondly, as cell capacitance is reduced, the sense-ampdifferential signal is reduced. This aggravates noise sensitivity andmakes it more difficult to design a sense-amp having appropriate signalselectivity. Thirdly, as cell capacitance is decreased, the cell refreshtime must generally be shortened, thus requiring more frequentinterruptions for refresh overhead. The difficult goal of a DRAMdesigner is therefore to increase or, at least, maintain cellcapacitance as cell size shrinks, without resorting to processes thatreduce product yield or that markedly increase the number of masking anddeposition steps in the production process.

[0005] Several methods for providing adequate cell capacitance in theface of shrinking cell size are either in use or under investigation.Basically, the efforts fall into two categories. Efforts within thefirst category are aimed at creating complex three-dimensionalcapacitors; those within the second are aimed at improving thedielectric of the planar capacitor.

[0006] One three-dimensional technique involves the creation of “trench”capacitors in the cell substrate. FIG. 2 depicts a DRAM cell having atypical trench capacitor 21. Similar in concept to planar capacitor 11of FIG. 1, the trench is employed to provide greater plate area, andhence, greater capacitance. The lower plate 22 may be formed from the n+doped silicon substrate or it may be formed from a polysilicon layerwhich lines a trench cut in the n+ doped silicon substrate. The upperplate 23 is formed from a layer of conductively-doped polycrystallinesilicon (poly). Lower plate 22 and upper plate 23 are electricallyinsulated from each other with a dielectric layer 24. DRAM chipsemploying trench capacitors have been built by a number of European,Japanese and U.S. companies, including IBM Corporation, TexasInstruments, Inc., Nippon Electric Company, Toshiba, Matsuchita andMitsubishi Electric Corporation. There are several problems inherent inthe trench design, not the least of which is trench-to-trench capacitivecharge leakage which is the result of a parasitic transistor effectbetween trenches. Another problem is the difficulty of completelycleaning the capacitor trenches during the fabrication process; failureto completely clean a trench will generally result in a defective cell.

[0007] Another three-dimensional technique, which is being used by mostDRAM manufactures including, Micron Semiconductor, Nippon ElectricCompany, Samsung, Goldstar, Hyundai, Mitsubishi Electric Corporation,Hitachi, and Fujitsu, Ltd., is the stacking of capacitor plates betweendielectric layers on the DRAM cell surface. FIG. 3 is a graphicrepresentation of a typical DRAM cell having a stacked capacitor 31. Thelower plate 32 is formed from an n-type polycrystalline silicon layerwhich is in contact with the silicon substrate 33 in the region of theFET storage node junction, while the upper plate 34 is formed from aconductively-doped polycrystalline silicon layer. The two layers areseparated by a dielectric layer 35. Lower or storage node plate 32 andupper plate 34 are both stacked on top of FET 12 and word line 36,resulting in a high-profile cell which requires more stringent processcontrol for the connection of bit line 37 to access-node junction 38.

[0008] In one variation of the stacked capacitor, which is currentlybeing used by National Electric Company, Micron, Samsung, Matsushita,and other DRAM manufacturers, the storage node plate of the stackedcapacitor is a rough polysilicon layer called hemispherical grain (HSG)polysilicon. This layer is formed at a critical temperature and pressureat which an anomalous nucleation occurs, causing the surface to roughen.The HSG polysilicon provides a much larger surface area than planarpoly. However the benefits of HSG polysilicon are not fully utilizedbecause the grains, as shown in an enlarged exaggerated cross-sectionalview in FIG. 4 of deposited HSG polysilicon 47, are so close togetherthat the dielectric layer 48 deposited to overlie the HSG polysilicon 47bridges between the grains. The dielectric layer 48 in the bridged areais often as thick as 400 angstroms. Therefore a method is needed toreduce the bridging of the dielectric 48 between the grains of the HSGpolysilicon 47 while maintaining the increased capacitive area providedby the HSG polysilicon 47.

SUMMARY OF THE INVENTION

[0009] The present invention is applicable to DRAM cell designs, such asthe stacked capacitor design heretofore described or a poly-lined trenchdesign, that utilize a conductively-doped polycrystalline layer for thestorage node, or lower capacitor plate. The invention is a method forforming HSG polysilicon with reduced dielectric bridging. A doped firstpolysilicon layer is deposited. A second polysilicon layer is thendeposited to overlie the first polysilicon layer. The temperature andpressure of the second polysilicon layer is selected in a range whereinHSG is formed during the deposition. Thus the surface of the secondpolysilicon layer is roughened as a result of nucleation. Next a wetetch is performed. The aggressiveness of the wet etch is controlled toremove portions of the rough polysilicon and portions of the basepolysilicon while retaining a roughened surface and maintaining a largesurface area of the storage node capacitor plate. The size of the grainsdecreases during the wet etch and the distance between the grainsincreases. A dielectric layer is deposited to overlie the roughpolysilicon following the wet etch. Bridging of the dielectric isreduced resulting in the dielectric layer having a uniform thicknessover the entire surface of the storage node capacitor plate. Sincebridging is reduced the thickness of the dielectric layer in areasformerly bridged is reduced and capacitance is increased.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a cross-sectional view of a DRAM cell having aconventional planar capacitor of the related art.

[0011]FIG. 2 is a cross-sectional view of a DRAM cell having a typicaltrench capacitor of the related art.

[0012]FIG. 3 is a cross-sectional view of a DRAM cell having a typicalstacked capacitor of the related art.

[0013]FIG. 4 is an exaggerated enlarged cross-sectional view of a DRAMstorage node capacitor plate and dielectric layer of the related art.

[0014]FIG. 5 is a cross-sectional view of a DRAM cell of a stackedcapacitor of the invention during the fabrication process subsequent tothe deposition of the storage node base polysilicon layer.

[0015]FIG. 6 is a cross-sectional view of the DRAM cell of FIG. 5following HSG polysilicon formation on the storage node base polysiliconlayer.

[0016]FIG. 7 is an exaggerated enlarged cross-sectional view of aportion of the nucleated polysilicon layer of FIG. 6.

[0017]FIG. 8 is a cross-sectional view of the DRAM cell of FIG. 6following a wet etch.

[0018]FIG. 9 is an exaggerated enlarged cross-sectional view of aportion of the nucleated polysilicon layer of FIG. 8.

[0019]FIG. 10 is a cross-sectional view of the DRAM cell of FIG. 8following the masking and etching of the base polysilicon layer and theHSG polysilicon layer.

[0020]FIG. 11 is a cross-sectional view of the DRAM cell of FIG. 10following the blanket deposition of a dielectric layer, the blanketdeposition of a polysilicon cell plate layer, and the masking of thecell plate layer.

[0021]FIG. 12 is an exaggerated enlarged cross-sectional view of aportion of the DRAM cell of FIG. 11.

[0022]FIG. 13 is a cross-sectional view of the DRAM cell of FIG. 11following the etching of the polysilicon cell plate layer and theformation of a bit line.

[0023]FIG. 14 is an exaggerated enlarged cross-sectional view of an HSGlayer of the related art following a deposition of a dielectric layer.

[0024]FIG. 15 a graph depicting capacitance data.

[0025]FIGS. 16A and 16B are thermal images of a storage node plate of aplanar capacitor after dielectric deposition. In FIG. 16A a wet etch wasnot performed and in FIG. 16B a wet etch was performed prior to thedielectric deposition.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0026] The invention is a method for forming a storage node capacitor. ADRAM cell 49 of stacked capacitor design is shown during the earlystages of the fabrication process. The storage node stacked capacitor ofthe invention is fabricated to overlie a wafer substrate 50 of intrinsicpolycrystalline silicon and to overlie a field oxide region 51 of thesubstrate 50. The cell's field-effect transistor (FET) 52 and wordline53 have already been formed. The FET gate 54 and wordline 53 are coveredon the top and sides by a silicon oxide spacer layer or nitride spacerlayer 55. A first or base polysilicon layer 57 is deposited over the FET52, the word line 53, the storage node junction 58, and the access nodejunction 59. The polysilicon layer 57 is then doped with phosphorus orother similar dopant to produce an extrinsic conductive polysiliconlayer.

[0027] Referring now to FIG. 6, a second polysilicon layer 58 isdeposited. The pressure and temperature during the deposition of thesecond polysilicon layer 58 is selected to induce nucleation therebyforming hemispherical grains 59 of polysilicon. The nucleated secondpolysilicon layer is called hemispherical grain (HSG) polysilicon. Thefirst 57 and second 58 polysilicon layers form the storage nodecapacitor plate of the storage node capacitor of the invention.

[0028] In an alternate method the HSG polysilicon is formed according tothe following process developed by Nippon Electric Company called vacuumanneal. In this process only one layer of doped or undoped amorphous orpolycrystaline silicon is deposited. The layer is subjected to a tightlycontrolled temperature and pressure to induce nucleation and form arough surface.

[0029]FIG. 7 is an exaggerated enlarged cross-sectional view of aportion 60 of FIG. 6. Although the actual grains 59 may not be perfectlyhemispherical as depicted in FIG. 7 they are configured similar to theexaggerated view of FIG. 7 and they tend to intersect one another at thesurface of the first polysilicon layer 57.

[0030]FIG. 8 is the DRAM cell of FIG. 6 following a wet etch. The wetetch can be either an oxide etch or a polysilicon etch. The etch removesportions of the grains 59 and portions of the first polysilicon siliconlayer 57. The size of the grains 59 decreases during the wet etch andthe distance between the grains 59 increases. By controlling theaggressiveness of the wet etch the large roughened surface area of theHSG polysilicon layer 58 is not only maintained it is enhanced therebyincreasing the surface area of the storage node capacitor plate.

[0031]FIG. 9 is the exaggerated enlarged cross-sectional view of aportion 60 of FIG. 8 depicting the smaller grains 58 and the increaseddistance between the grains 59 following the wet etch.

[0032] In FIG. 10 the first polysilicon layer 57 and the secondpolysilicon layer 58 are masked with mask 66 and etched in unmaskedregions to define the storage node capacitor plate comprising first andsecond polysilicon layers 57 and 58.

[0033] In an alternate embodiment it is equally effective to perform thewet etch after the masking, etching and subsequent mask removal in orderto form the storage node portion having smaller grains and an increaseddistance between the grains.

[0034] In FIG. 11 a dielectric layer 69 having good step coverage isdeposited to overlie first 57 and second 58 polysilicon layers.Typically the dielectric layer 69 is silicon nitride having a thicknessof approximately 80 Angstroms, although other dielectric materials andthicknesses may be used. Due to the decreased size of the grains 59 andthe increased distance between the grains 59 the thickness of thedielectric layer 69 is approximately uniform. The dielectric depositionis followed by the blanket deposition of a polysilicon cell plate layer70, the conductive doping of cell plate layer 70 with phosphorus orother similar dopant, and the masking of the cell plate layer 70 withphotomask 71.

[0035]FIG. 12 is the exaggerated enlarged cross-section of portion 60 ofFIG. 11. It can be seen that the thickness of the dielectric layer 69 isuniform, in this example 80 angstroms, over 100% of the surface of thesecond polysilicon layer 58 and over 100% of the surface of exposedportions of the first polysilicon layer 57.

[0036] Referring now to FIG. 13, cell plate layer 70 and dielectriclayer 69 have been etched forming the stacked capacitor of theinvention. The process is completed with a conformal deposition of oxide74 etched to expose access node junction 59. A bit line 76 is thendeposited and patterned to contact the access node junction 59.

[0037]FIG. 14 is a depiction of the related art and is provided in orderthat the storage node capacitor plate and dielectric layer of theinvention, as shown in FIG. 12, can be compared to a storage nodecapacitor plate and dielectric formed without the wet etch of thepresent invention. FIG. 14 is an exaggerated enlarged cross-section ofan unetched HSG polysilicon layer 80 with an overlying dielectric layer85. Even though the minimum thickness of the dielectric layer 85 is 80angstroms, as is the dielectric layer 69 shown in FIG. 12, thedielectric bridges over the intersections 90. Therefore the dielectricinterposed between two adjacent grains 95 is much thicker than 80Angstroms. This results is less surface area being covered by dielectrichaving the minimum thickness. The distance covered by the dielectric 85having minimum thickness is represented by the surface of the HSGpolysilicon 80 interposed between points 95 and 100.

[0038] Thus by using the method of the invention the percentage of thesurface area covered by a minimum thickness of dielectric can reach100%. In some instances this 100% coverage is a 38% increase overmethods which do not employ the wet etch of the invention. Therefore byusing the method of the invention capacitance can be increased by atleast between 10% and 50%.

[0039]FIG. 15 is a graph showing the relationship between capacitanceand etch time. The etch time is measured in minutes and the capacitanceis measured in pico farads. The capacitance of each point A-G wascalculated by averaging the results obtained on 10 different capacitors,each capacitor having an area of 6400 square microns. All possiblevariables such as size of the storage node plate, size of the cell plateand thickness of the dielectric were held constant throughout theexperiment. Point A shows that the capacitance of a capacitor comprisinga doped polysilicon layer without an overlying HSG layer as the storagenode plate is between 42 and 43 pico farads. Points B-G show thecapacitance of a capacitor having a doped polysilicon layer andoverlying HSG layer as the storage node plate. At point B where the HSGwas not etched the capacitance is between 56 and 57 pico farads.Capacitance increases as etch time for etching the HSG layer increasesand starts to level off at point F after 15 minutes of etching. At pointF the capacitance is between 78 and 79 pico farads, although data wasnot obtained for capacitors having etch times between 10 and 15 minutes.Over etching that reduces the roughness of the HSG layer couldeventually reduce the capacitance to the range of capacitanceexperienced when no HSG layer is provided. Therefore the etch must becontrolled to optimize capacitance.

[0040]FIGS. 16A and 16B are thermal images of a storage node plate of aplanar capacitor after dielectric deposition. In FIG. 16A a wet etch wasnot performed and in FIG. 16B a wet etch was performed prior to thedielectric deposition. The separation of the grains is more evident whenthe wet etch has been performed.

[0041] The invention may also be implemented wherein the stackedcapacitor is fabricated overlaying the bit lines or for other types ofcapacitors, such as trench. Monocrystalline silicon may also be used inplace of polycrystalline.

[0042] By decreasing the size of the grains and increasing the distancebetween them during the wet etch the maximum thickness of the dielectriclayer is decreased thereby increasing capacitance.

[0043] Although the invention has been described in terms of one methodfor masking and forming a stacked capacitor the invention is equallyapplicable for any method of forming a capacitor comprising wet etchinga nucleated polysilicon layer.

[0044] Although only a single embodiment of the invention has beendescribed herein, it will be apparent to one skilled in the art thatchanges and modifications may be made thereto without departing from thespirit and the scope of the invention as claimed.

What is claimed is:
 1. A method for forming a capacitor, comprising thefollowing steps: a) forming a polysilicon layer having a hemisphericalgrained surface overlying a substrate; b) etching said polysilicon layerto decrease a size of said grains and to increase a distance betweensaid grains; and c) forming a dielectric layer to overlie saidpolysilicon layer.
 2. The method as specified in claim 1 , furthercomprising the step of forming a cell plate layer to overlie saiddielectric layer, said polysilicon layer being a storage node capacitorplate of the capacitor.
 3. The method as specified in claim 2 , furthercomprising the step of doping said cell plate layer to increase aconductivity thereof.
 4. The method as specified in claim 1 , whereinsaid step of forming said polysilicon layer comprises depositing saidpolysilicon layer at a temperature and pressure that forms hemisphericalgrains of said polysilicon layer.
 5. The method as specified in claim 1, wherein said step of forming said dielectric layer comprisesdepositing a dielectric material to have a uniform thickness.
 6. Amethod for forming a capacitor, comprising the following steps: a)providing a granulated first capacitive storage plate having a pluralityof grains on a surface thereof; b) decreasing a size of said grains; c)increasing a distance between said grains; d) forming a dielectric layerto overlie said first capacitive storage plate; and e) forming a secondcapacitive storage plate overlying said dielectric layer.
 7. The methodas specified in claim 6 , wherein said step of forming said dielectriclayer comprises depositing a conformal dielectric material to overliesaid first capacitive storage plate.
 8. The method as specified in claim6 , further comprising the step of performing a wet etch to removeportions of said grains in order to effect said steps of increasing anddecreasing.
 9. A method for forming a capacitor, comprising thefollowing steps: a) forming a base layer to overlie a substrate, saidbase layer functioning as a storage node capacitor plate of saidcapacitor; b) adjusting a temperature and pressure of said base layer inorder to cause a nucleation of said base layer; c) forming grains ofsaid base layer on a surface of said base layer during said step ofadjusting; d) performing a wet etch of said base layer to decrease asize of said grains and increase a distance between said grains; e)controlling a duration of said wet etch to control a surface area ofsaid base layer remaining subsequent to said wet etch; f) forming adielectric layer to overlie said base layer; and g) forming a cell platelayer to overlie said dielectric layer, wherein said base layer, saiddielectric layer and said cell plate layer form said capacitor.
 10. Amethod for forming a capacitor, comprising the following steps: a)forming a first polysilicon layer overlying a substrate; b) forming asecond polysilicon layer having hemispherical grains overlying saidfirst polysilicon layer; c) etching at least said second polysiliconlayer to decrease a size of said grains and increase a distance betweensaid grains; and d) forming a dielectric layer to overlie at least saidsecond polysilicon layer.
 11. The method as specified in claim 10 ,further comprising forming a cell plate layer to overlie said dielectriclayer, said first and said second polysilicon layers forming a storagenode capacitor plate of said capacitor.
 12. The method as specified inclaim 11 , further comprising doping said cell plate layer and saidfirst polysilicon layer to increase conductivities thereof.
 13. Themethod as specified in claim 10 , wherein said step of forming saidsecond polysilicon layer comprises depositing said second polysiliconlayer at a temperature and pressure to form said hemispherical grains insaid second polysilicon layer.
 14. The method as specified in claim 10 ,wherein said step of forming said dielectric layer comprises depositinga dielectric material to have a uniform thickness.
 15. The method asspecified in claim 10 , further comprising etching said firstpolysilicon layer to remove portions thereof and to further increasesaid distance between said grains.
 16. A method for forming a capacitor,comprising the following steps: a) depositing a first polysilicon layerto overlie a substrate; b) doping said first polysilicon layer toincrease a conductivity thereof; c) depositing a second polysiliconlayer to overlie said first polysilicon layer; d) adjusting atemperature and pressure of said second polysilicon layer in order tocause a nucleation thereof; e) forming hemispherical grains of saidsecond polysilicon layer during said step of adjusting; f) performing awet etch on said second and portions of said first polysilicon layers todecrease a size of said grains and increase a distance between saidgrains; g) forming a dielectric layer to overlie said first and saidsecond polysilicon layers; and h) forming a cell plate layer to overliesaid dielectric layer, wherein said first and said second polysiliconlayers comprise a storage node plate of said capacitor.
 17. The methodas specified in claim 16 , further comprising controlling a duration ofsaid wet etch to control a surface area of said first and said secondpolysilicon layers remaining subsequent to said wet etch.